/**
 * Introduction
 * 介绍
 *
 * Well most of the changes in Verilog 2001 are picked from other languages, like generate, 
 * configuration, file operation were from VHDL. I am just adding a list of the most commonly 
 * used Verilog 2001 changes. You may need a simulator with Verilog 2001 support for testing the 
 * examples listed below.
 *
 * Verilog 2001中的大部分变化都来自于其他语言，比如生成、配置、文件操作都来自于VHDL。我只是添加了一个最常用
 * 的Verilog 2001变化的列表。您可能需要一个支持Verilog 2001的模拟器来测试下面列出的示例。
 *
 * Comma used in sensitive list
 * 在敏感列表中使用逗号
 *
 * In earlier version of Verilog ,we used to use 'or' to specify more than one sensitivity list element. 
 * In the case of Verilog 2001, we use comma as shown in the example below.
 * 
 * 在Verilog的早期版本中，我们使用'or'来指定多个敏感性列表元素。在Verilog 2001中，我们使用逗号，如下例所示。
 */

module comma_example();

reg a, b, c, d, e;
reg [2:0] sum, sum95;

// Verilog 2k example for usage of comma
// Verilog 2k逗号用法示例
always @ (a, b, c, d, e)
begin : SUM_V2K
  sum = a + b + c + d + e; 
end

// Verilog 95 example for above code
// 以上代码的Verilog 95示例
always @ (a or b or c or d or e)
begin : SUM_V95
  sum95 = a + b + c + d + e; 
end

initial begin
  $monitor ("%g a=%b b=%b c=%b d=%b e=%b sum=%b sum95=%b", 
    $time, a, b, c, d, e, sum, sum95);
  #1 a = 1;
  #1 b = 1;
  #1 c = 1;
  #1 d = 1;
  #1 e = 1;
  #1 $finish;
end

endmodule
